I'M Intelligent Memory ECC DRAM components come with an integrated ECC error correction algorithm that detects and corrects single-bit errors on the fly, elevating your application to new levels of memory reliability as known from servers.
ECC DRAMs are direct drop-in-replacements for conventional DRAMs and do not require any software or hardware adaptions. The data-correction is performed by the DRAM itself without any noticable delays or latencies, and completely independent from the processor.
Customers using the I'M ECC DRAM may promote their applications utilizing the I'M ECC Protected badge.
We offer our ECC DRAM products with operation temperature ranges up to 125° C (X-Grade). Optionally with Grade 1 AEC-Q100 qualification.
* C = Commercial Temp, I = Industrial Temp, H = High Temp, X = Extreme Temp
ECC DRAMs are memory components with integrated error-correction logic. The ECC DRAMs internally generate parity-data for each data-block of 64 bit which allow to detect and correct single bit errors within each 64-bit internal data-block. As an example, a 1 Gigabit ECC DRAM internally consists of 16 million blocks of 64 bit. Even in the extremely rare case that each and every block would have a single bit error, the DRAM would still work perfectly as the ECC algorithm will correct all these errors. The error-correction algorithm is identical to what is used on server-memory-modules, but servers perform this algorithm by the CPU, while the ECC DRAMs perform the algorithm in the DRAM-chip itself. This is why ECC DRAMs make it possible to add a 'server level memory reliability' to any application, even if the CPU on your application is unable to perform ECC-correction.
With the ECC DRAM we did not change the technology used to manufacture the memory-array of the DRAMs, but we added a validation and correction algorithm to the device-internal logic.
Intelligent Memory´s ECC eXtra Robust DRAM components utilize a physical protection to the stored data-bits by holding the bits in larger capacitors, with a redundant data topology combined with built-in error correction features.
Each databit of a DRAM is stored in a very small capacitor holding a minimal electron-charge that defines the databit to be Zero or One. The data-integrity completely depends on these little capacitor-charges. On eXtra Robustness ECC DRAM each two cells are being 'twinned' to hold one databit, doubling the total electron-charge. As a result, the retention-time of each cell increases exponentially. Even increased leakage after cell-degradation does not cause a data-loss anymore as there is a much higher charge in each cell. External influences through radiation, antennas, etc can hardly flip the databits any more. The signal-margins (difference of charge-level for a Zero or a One) are much greater.
The eXtra Robustness (XR) DRAMs also have the ECC error correction functionality. In the very rare case that an XR ECC DRAM should have a bit-flip, the error-correction will catch and correct it. They are the most reliable DRAMs available.