Introducing I'M Intelligent Memory's ECC DRAM and ECC eXtra Robust DRAM components built with integrated ECC error correction.

The on die algorithm corrects single bit errors on the fly, elevating your application to new levels of memory reliability previously only attainable in servers. The eXtra Robust DRAM components utilize a physical protection to the stored data-bits by holding the bits in larger capacitors, with a redundant data topology combined with built-in error correction features.

Intelligent Memory's ECC DRAM and ECC eXtra Robust DRAM components are drop-in replacements for conventional DRAM chips and do not require hardware or software changes to function. The data correction is performed within the chip itself without noticeable delays or latencies and completely independent of a processor.

We offer our ECC DRAM and eXtra Robust DRAM products with operation temperature ranges up to 125° C (X-Grade). Please contact us for AEC-Q100 Grade 1 qualified parts.

Customers using the I'M ECC and ECC eXtra Robust DRAM components may promote their application utilizing the I'M ECC protected badge.



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The Industrial temperature grade is readily available for every product. These parts get extensively tested to achieve not only the temperature range, but also a high reliability. Higher temperature ranges like 105°C or automotive graded products will be handled upon request. Manufacturing these special temperature and quality grades is generally possible, but requires a requalification, extended testing and comes with a yield-loss in production. We can at any time start this process for customers with such a specific demand. Please contact us.

The typical effects seen at higher temperature operation of DRAMs are that the number of 'retention-fails' increases, resulting in single bit errors.

Our ECC DRAM product line contains an error correction logic which automatically corrects such errors before outputting the data. All ECC DRAMs are factory-tested at the specified temperature-range with the error-correction logic turned OFF to make sure that all memory-cells are running perfectly well. Higher temperatures can result in single bit errors in the DRAM, but as per 1 Gigabit of ECC DRAM there are 16 Million single-bit-correctable data-blocks, the ECC DRAMs will continue outputting correct data even at much higher operating temperatures than specified in the datasheet.

This refers to the number of chip-select and control-lines of the device. The majority of standard DRAMs use only one set of control lines, they have just one chip-select line. To achieve higher memory capacities, the JEDEC standard specification allows to put multiple memory 'dies' into one package, while each die has a separate set of control lines. For example a DDR3 component with a capacity of 8 Gigabit and "2CS" has two separate sets of control lines, so each 4 Gigabit can be separately activated and accessed. For these additional control lines - chip select, clock enable, ODT, ZQ - there are extra pin-contacts used, which are normally 'NC - not connected' on standard devices with single chip select.

But Intelligent Memory also offers such 8 Gigabit DDR3 devices with just one set of control lines, single chip-select. These do not show "2CS" under Organization, use no additional pins and fit onto most applications without having to change the layout.

As a matter of fact, DRAMs are not perfect, they will have single-bit errors from time to time which can cause malfunctions, data corruption or system crashes. Please check out our ECC DRAM product line. These products are automatically verifiying and correcting the DRAM data output by an integrated error correction logic, very similar to what is used on High End Servers. Please also read the ECC DRAM FAQs.

Product Brief

DRAM with integrated error correcting code

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