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Flash Memory is a non volatile electrically erase- and programmable type of semiconductor memory.

Serial Peripheral Interface (SPI) is an interface bus commonly used to send data between microcontrollers and small peripherals device.

eMMC (embedded Multimedia Card) is a "managed Flash" - Media i.e. Flash-Controller and raw Flash Memory are combined in one common BGA Package. The raw flash management is handled by the Flash controller thus the eMMC user must not take care about bad block management, ecc, wear leveling etc.

MLC means Multi Level Cell. In a MLC two data Bits are keept in one Flash cell. Two Data bits require 4 voltage levels to be maintained in one cell which are detected by comparators. Advantage is a higher Bit density but on the expense of smaller voltage margins in comparison to Single Level Cells (SLC) where one needs to detect only two voltage levels - chareged / non-charge.

In a NOR Flash the cells are organised in a kind of "parallel array" structure each cell can directly accessed by the internal logic thus the device can be operated in a Byte wise manor. This is good for program code for instance. In comparison to this in NAND Flash the cells are connected in a "serial array" structure thus there are page and block accesses required. This is good for fast data storage and handling. The parallel oriented NOR structure requires a for more complex internal connection than a NAND structure thus NOR is more costly than NAND per bit.

NAND Flash is organised in blocks. It is typically in use with Applications where bigger Data quantities have to be written and read in a fast manner.

The pSLC configuration on muliti level cell ( MLC, TLC) NAND only takes 2 bits for data storage from original 4bit MLC or 8 bits TLC NAND. It can dramatically increase the reliability, endurance of NAND Flash. It makes the SSDs meet high P/E cycle, high TBW demand in industrial and embedded applications and also increases data access performance.

SerialATA Bus is a serial interface widely used to connect Hard Disk or alike flash based Storages (SSD´s) to the main control unit like the PC motherboard for instance.

QLC means Quadruple Level Cell but it is meant that 4 Bit of data are keept in one Cell. To keep all information which can be represented by 4 bit one needs actually to maintain savely 16 different voltage levels in one cell. These voltages are detected by comparators and by logic in the device and represent the 4 bit information of each cell. Advantage is high data density per chip but the trade of is weaker data integrity so this technology requires ECC for reliable data retention.

SSD stands for Solid State Disk - which means a storage device being based on solid state (or semiconductor) typically Flash based memory. There is actually no "disk" used as in mechanical Hard disk drives which have rotating disks storing the data in magnetic particles. A SSD stores the data in raw Flash components which are managed by a Flash controller which communicates to the Main Units (Motherboard) by a interface like SATA, PCIe etc.

RAW NAND comes without error collection mechanism and cell life time management, it requires an external host controller to perform the management of previous functions.

Managed NAND like eMMC and SPI NAND contain a built-in controller module, and by design it can handle the ECC requirements of theRAW NAND. Firmware to handle the ECC strategies (performs retry, block bad identification, and replacement) is built in to memory media; this must be provided in the software layer for raw flash.

SPI NAND consists of RAW NAND Flash and a controller providing bad block management, wear leveling of NAND and communication with Host through SPI interface.

SPI NAND provides low pin count and smaller dimension compared to parallel NAND Flash, which saves design cost and PCB cost of system. The controller of SPI NAND can manage error correction and bad block replacement, it also saves loading of host SOC.

Intelligent Memory (IM) supplies LGA8 6x8mm 8pins package SPI NAND.

1. SPI NAND 's R/W Performance is good enough for boot device rather than large storage

2. SPI NAND can handle ECC and FW complexity, which is easier for SoC to control

3. Overall BOM cost can be reduced in comparison to Parallel NAND

Data Retention is the capability of retaining stored information over time. The Data Retention Time is the period of time the memory can "retain" data in an unbiased condition. Also, data retention time is a function of P/E cycles and temperature. On the other side, NAND Flash Endurance and TBW highly depend on data retention period required.

Yes, there are many successful applicaion implemened SPI NAND such as Set Top Box, Wi-Fi Router, Surveillance Camera, NVR, Smart Home devices...

TBW (Terabytes Written) is a measurement of SSDs' expected lifespan, which represents the amount of data written to the device.