Intelligent Memory Limited is a fabless memory manufacturer serving the industrial electronics market. Founded in Hong Kong in 1991, Intelligent Memory has seen steady growth over two more decades. Intelligent Memory serves a wide range of medium to large size OEMs.
Most memory manufacturers have identical products and only compete by price. They focus on mass-market products to be able to 'move' millions of standard components at low cost.
At Intelligent Memory, we care about the industrial market and their special demands on reliability, extended temperature ranges, long lifetime, wide databus and high density components. We utilize own unique technologies and experience to achieve these goals at attractive pricing, also for customers with smaller production volumes.
Please try to use our cross-reference search or send us an email. We will let you know if our products are compatible.
The Industrial temperature grade is readily available for every product. These parts get extensively tested to achieve not only the temperature range, but also a high reliability. Higher temperature ranges like 105°C or automotive graded products will be handled upon request. Manufacturing these special temperature and quality grades is generally possible, but requires a requalification, extended testing and comes with a yield-loss in production. We can at any time start this process for customers with such a specific demand. Please contact us.
The typical effects seen at higher temperature operation of DRAMs are that the number of 'retention-fails' increases, resulting in single bit errors. We have a very special product line called ECC DRAM which was developed for the companies who have very high concern on reliability or high temperature operations. Our ECC DRAM product line contains an error correction logic which automatically corrects such errors before outputting the data. All ECC DRAMs are factory-tested at the specified temperature-range with the error-correction logic turned OFF to make sure that all memory-cells are running perfectly well. Higher temperatures can result in single bit errors in the DRAM, but as per 1 Gigabit of ECC DRAM there are 16 Million single-bit-correctable data-blocks, the ECC DRAMs will continue outputting correct data even at much higher operating temperatures than specified in the datasheet.
This refers to the number of chip-select and control-lines of the device. The majority of standard DRAMs use only one set of control lines, they have just one chip-select line. To achieve higher memory capacities, the JEDEC standard specification allows to put multiple memory 'dies' into one package, while each die has a separate set of control lines. For example a DDR3 component with a capacity of 8 Gigabit and "2CS" has two separate sets of control lines, so each 4 Gigabit can be separately activated and accessed. For these additional control lines - chip select, clock enable, ODT, ZQ - there are extra pin-contacts used, which are normally 'NC - not connected' on standard devices with single chip select.
But Intelligent Memory also offers such 8 Gigabit DDR3 devices with just one set of control lines, single chip-select. These do not show "2CS" under Organization, use no additional pins and fit onto most applications without having to change the layout.
As a matter of fact, DRAMs are not perfect, they will have single-bit errors from time to time which can cause malfunctions, data corruption or system crashes. Please check out our ECC DRAM product line. These products are automatically verifiying and correcting the DRAM data output by an integrated error correction logic, very similar to what is used on High End Servers. Please also read the ECC DRAM FAQs.
ECC DRAM is a completely concept to the market. It is a special product line developed for the companies who have high concern on the reliability or high temperature operations.
ECC DRAMs are memory components with integrated error-correction logic. The ECC DRAMs internally generate parity-data for each data-block of 64 bit which allow to detect and correct single bit errors within each 64-bit internal data-block. As an example, a 1 Gigabit ECC DRAM internally consists of 16 million blocks of 64 bit. Even in the extremely rare case that each and every block would have a single bit error, the DRAM would still work perfectly as the ECC algorithm will correct all these errors. The error-correction algorithm is identical to what is used on server-memory-modules, but servers perform this algorithm by the CPU, while the ECC DRAMs perform the algorithm in the DRAM-chip itself. This is why ECC DRAMs make it possible to add a 'server level memory reliability' to any application, even if the CPU on your application is unable to perform ECC-correction.
Yes, they are 100% fit/form/function compatible to conventional DRAMs according to the JEDEC specifications. They will work as drop-in-replacement without any changes to your hardware or software. Also there is no timing-difference to conventional DRAM. The error-correction logic of the ECC DRAMs is extremely fast, thus there are no additional delays or latencies compared to the JEDEC standard specifications.
Please try our Cross Reference Search to find replacements for the part you are currently using.
Yes, absolutely. If you assemble your board with ECC DRAMs instead of using conventional DRAMs, you will immediately have the error-correction functionality.
Fact is: DRAM components are not perfect. Some databits inside every DRAM will flip from 0 to 1 or from 1 to 0 from time to time. There are multiple analyses and statistics about how often bit-flips in DRAMs occur, but none of them can be used universally for all applications. One interesting research comes from the University of Toronto, which is called 'DRAM Errors in the Wild - A large scale field study'. This study monitored the DRAM errors in the thousands of systems of the famous Google server-farm for a period of 2 1/2 years. All those servers were surely perfectly air-conditioned, dust-free and protected from radiations of all kinds. Still they came to the result of 25,000 to 70,000 FIT (failures per billion device hours) of 'ECC correctable errors' per Megabit of DRAM. This converts into an average of one single-bit-error every 14 to 40 hours per Gigabit of DRAM.
The field study also explains that the error-rate increases by the age of the memory. Brand new DRAMs might not show any errors for weeks and months, but then the error-rate suddenly goes up.
Uncorrectable errors could be double- or multi-bit errors or complete functional fails of the DRAM. These can all not be corrected, but are extremely rare.
A 1 Gigabit ECC DRAM contains 16 Million blocks of 64 bit datawords. Per each of these 64 bit words, one error is correctable. In other words: Statistically one out of 16 million hits might be a double-bit error. If one error hits per day, this would mean that it takes hypothetically 16 Million days or 48000 years for a double-bit error to hit. But this is just the maths. Finally the real numbers depend on the stress and the environment the application is running in.
DRAM errors are transient. They come and go. Look at the electronics in your household. Everybody knows the blue-screen of computers. Navigation systems sometimes suddenly hanging up or showing weird things on the screen. The WiFi router sometimes does not want to connect to the internet any more or repeatedly asks you for your WiFi password, although you entered it correctly. After a Reset/Reboot these application work fine again. In most cases a "single event effect" like a DRAM single-bit-error was the root-cause. Do you return your device to the manufacturer just because you had a non-repeatable problem that got solved after a Reset/Reboot? I guess the answer is No, but still it is annoying.
But not every error results in a system crash. If the error hits into graphics, audio data or unused DRAM areas, the user typically does not even notice it. When the error hits important data, calculations or the program function might be corrupted. The worst scenario is a hit into the program-code.
Real 'defects' of DRAM components are extremely rare. The majority of problems are single-event-'effects' which the customers can not repeat again.
On a server, for example, the customers expect them to run 24 hours a day, 365 days a year. This is why server-CPUs are equipped with an ECC logic and require special 72 bit wide memory-modules that can store 8 parity bits additional to the 64 databits for every access.
You better use error-correction whenever you want your product to be running stable, even after months and years of use, even when people put their cellphone right onto it (disturbance from the antenna) or when the sun heats the product up.
There are many root causes. A major factor is that the memory-cells in the DRAM have slight weaknesses and cause a bit-flip. But even those weak cells are not permanently damaged. The cell might work fine for a million or more accesses and then suddenly loses its data one time, not repeatable. You can only find out it is a weakness by noticing that the same databit-cell is affected again by an error after some time.
DRAMs also suffer from aging, they degrade. The isolations of some single bit-cells get weaker and the leakage increases. Single bit errors suddenly appear although there never has been such problem in the past.
Radiation of any kind can influence the DRAM cells. Even the natural ambient radiation we have on earth is able to flip a bit in a DRAM. The higher above sea-level, the stronger is the radiation.
Also antennas, for example from Cellphones, can disturb right into the memory-cells of a DRAM.
Heat is a big issue for memory-components. As a DRAM stores the data in little capacitors which have a certain leakage anyway, higher temperatures cause an increased leakage and at some point the first one or two memory-cells lose their data before they get refreshed by the CPU. We call this a 'retention-fail'.
Running DRAMs constantly under high temperatures or radiation accelerates the degradation of the products.
It depends on your CPU bus-width and the DRAM bit-width, because every single ECC DRAM IC will perform its individual error-correction. For example, if your CPU has a 64 bit wide memory-bus and you use 8 pieces of ECC DRAMs in a x8 organization, you will have total eight error-corrections running in parallel. This way even multiple single-bit errors within the 64 databits will be correctable (one per component).
Let's compare this to the error-correction as it is done on servers and other applications by the CPU: If the CPU is ECC-capable, it typically has a 72 bit wide memory bus. 9 pieces of DRAMs in a x8 configuration or 18 pieces of DRAMs in a x4 organization have to run in parallel. But all over the total 72 databits, only one bit can be corrected by the CPU-internal ECC.
Conclusion: In the majority of applications multiple DRAMs are connected to the memory-bus of the CPU in parallel. Using ECC DRAMs is much more effective than the CPU-controlled-ECC due to the fact that every single ECC DRAM can perform an individual error-correct, which multiplies the effectiveness.
PS: It would even be possible to use ECC DRAMs together with an ECC-capable CPU. This way each ECC DRAM performs a correction and the CPU will do another final check and correction of the data.
It depends on the reliability you expect from your application. You decide if you can accept the risk of data-corruption, malfunction or crash to happen on your application or not.
Todays conventional DRAMs used in simple game-computers are identical to the DRAMs used in high-end industrial applications. Same part numbers, same products. For automotive applications the DRAM-manufacturers perform a more extensive test process, but even those 'AEC-Q100' qualified DRAMs are still having no protection from disturbing external influences, also they can degrade or react sensitive to line-noise, etc. Stronger quality-testing is no guarantee to have no single-bit errors.
ECC DRAMs are pin-compatible to conventional DRAMs, thus they can also be put onto any memory-module PCB, lifting these modules to an unparalleled reliability. Any application taking DIMMs, SO-DIMMs, Mini DIMMs or other form factors can take advantage of the ECC protection, no matter if the CPU supports ECC or not.
Memory modules typically are 64 or 72 bits wide and are made of multiple DRAMs (with x4 or x8 bit-width) running in parallel. Since every single ECC DRAM performs its own error-correction algorithm, a module built with ECC DRAMs can perform multiple data-verifications & corrections in parallel. Even 72 bit wide modules used on applications that perform ECC by the CPU would be able to add multiple levels of reliability.
Any memory-module manufacturing company can build modules based on ECC DRAMs. Our distribution-partner Memphis Electronic produces memory-modules for the industry for many years and has a portfolio of multiple hundreds different module-designs. Please contact them at email@example.com with your memory-module demands.
With the ECC DRAM we did not change the technology used to manufacture the memory-array of the DRAMs, but we added a validation and correction algorithm to the device-internal logic.
Intelligent Memory´s ECC eXtra Robust DRAM components utilize a physical protection to the stored data-bits by holding the bits in larger capacitors, with a redundant data topology combined with built-in error correction features.
Each databit of a DRAM is stored in a very small capacitor holding a minimal electron-charge that defines the databit to be Zero or One. The data-integrity completely depends on these little capacitor-charges. On eXtra Robustness ECC DRAM each two cells are being 'twinned' to hold one databit, doubling the total electron-charge. As a result, the retention-time of each cell increases exponentially. Even increased leakage after cell-degradation does not cause a data-loss anymore as there is a much higher charge in each cell. External influences through radiation, antennas, etc can hardly flip the databits any more. The signal-margins (difference of charge-level for a Zero or a One) are much greater.
The eXtra Robustness (XR) DRAMs also have the ECC error correction functionality. In the very rare case that an XR ECC DRAM should have a bit-flip, the error-correction will catch and correct it. They are the most reliable DRAMs available.
Yes, we definitely work on that. If you have an interesting high volume project for which you would like to use ECC DRAM, please contact us.
We have to diversify between standard computer systems (laptops, desktops, servers) and industrial applications.
Most standard computer systems base either on Intel or AMD processors. We verified that most AMD CPU based computers work fine with 16GB modules. For Intel-CPU based systems, the compatibility is currently limited to the new Intel 5th generation 'Broadwell' CPUs (i3/i5/i7-5xxxU), which are used in many notebooks and NUCs since year 2015. In addition, there are many small server platforms running on Intel Atom 'Avoton' C2xxx processors, for example from Supermicro or ASRock, which have been approved with Intelligent Memory 16GB modules as well.
Embedded/Industrial applications typically use CPUs or FPGAs which allow the memory to be manually configured, for example from Freescale, TI, Xilinx, etc. These platforms will all work fine with IM 16GB modules. For Intel based boards, the compatibility has been verified for 5th generation Broadwell-U and 'Baytrail-I' E38xx processors, as long as the latest MRC is used in the BIOS.
In early 2015, Intel has released the new 5th generation Broadwell-U CPUs, which can be identified by the CPU code i3/i5/i7-5xxxU. The '-5' in the CPU-code defines the processor-generation to be the 5th. The majority of Laptops, NUCs and other platforms with these new 5th gen CPUs have already been successfully tested to take the Intelligent Memory 16GB SO-DIMMs. Machines with two memory-slots can be upgraded to 32GB by using two 16GB modules. However, even if your notebook has a 5th generation Intel CPU, you will often find the official manufacturer specification to show a maximum memory of only 8GB (single memory slot) or 16GB (two memory slots). As we understand that this is very confusing, please check our compatibility list and additionally contact us to verify if your laptop or NUC is compatible before you place your order.
The new Apple 27" iMac (release Oct 2015) are based on 6th Gen Intel® Core™ Processor Platform (code name "Skylake"). These machines can use our 16GB DDR3 SODIMMS ( IMM2G64D3(L)SOD8A) so by using all 4 slots with these modules you can reach up to 64GB main memory.
Important: Notebooks or other systems with Intel 3rd, 4th or older CPU-generations are unfortunately not able to take 16GB modules. Please do not order 16GB modules just to 'try them'. We can assure you that older Intel based platforms can not recognize the memory and will not boot.
Please click Where-to-buy to find your next local dealer or distributor. Intelligent Memory is very interested to partner with more online-shops, computer dealers and system-integrators worldwide. If you have your own preferred reseller where you purchased your notebook, NUC or server, please inform this reseller to send an e-mail to firstname.lastname@example.org to request pricing, product information and marketing material. WIth your help, we can expand our sales-network and you can get local support!
Flash Memory is a non volatile electrically erase- and programmable type of semiconductor memory.
eMMC (embedded Multimedia Card) is a "managed Flash" - Media i.e. Flash-Controller and raw Flash Memory are combined in one common BGA Package. The raw flash management is handled by the Flash controller thus the eMMC user must not take care about bad block management, ecc, wear leveling etc.
MLC means Multi Level Cell. In a MLC two data Bits are keept in one Flash cell. Two Data bits require 4 voltage levels to be maintained in one cell which are detected by comparators. Advantage is a higher Bit density but on the expense of smaller voltage margins in comparison to Single Level Cells (SLC) where one needs to detect only two voltage levels - chareged / non-charge.
In a NOR Flash the cells are organised in a kind of "parallel array" structure each cell can directly accessed by the internal logic thus the device can be operated in a Byte wise manor. This is good for program code for instance. In comparison to this in NAND Flash the cells are connected in a "serial array" structure thus there are page and block accesses required. This is good for fast data storage and handling. The parallel oriented NOR structure requires a for more complex internal connection than a NAND structure thus NOR is more costly than NAND per bit.
The pSLC configuration on muliti level cell ( MLC, TLC) NAND only takes 2 bits for data storage from original 4bit MLC or 8 bits TLC NAND. It can dramatically increase the reliability, endurance of NAND Flash. It makes the SSDs meet high P/E cycle, high TBW demand in industrial and embedded applications and also increases data access performance.
QLC means Quadruple Level Cell but it is meant that 4 Bit of data are keept in one Cell. To keep all information which can be represented by 4 bit one needs actually to maintain savely 16 different voltage levels in one cell. These voltages are detected by comparators and by logic in the device and represent the 4 bit information of each cell. Advantage is high data density per chip but the trade of is weaker data integrity so this technology requires ECC for reliable data retention.
NAND Flash is organised in blocks. It is typically in use with Applications where bigger Data quantities have to be written and read in a fast manner.
SerialATA Bus is a serial interface widely used to connect Hard Disk or alike flash based Storages (SSD´s) to the main control unit like the PC motherboard for instance.
SSD stands for Solid State Disk - which means a storage device being based on solid state (or semiconductor) typically Flash based memory. There is actually no "disk" used as in mechanical Hard disk drives which have rotating disks storing the data in magnetic particles. A SSD stores the data in raw Flash components which are managed by a Flash controller which communicates to the Main Units (Motherboard) by a interface like SATA, PCIe etc.
RAW NAND comes without error collection mechanism and cell life time management, it requires an external host controller to perform the management of previous functions.
Managed NAND like eMMC and SPI NAND contain a built-in controller module, and by design it can handle the ECC requirements of theRAW NAND. Firmware to handle the ECC strategies (performs retry, block bad identification, and replacement) is built in to memory media; this must be provided in the software layer for raw flash.
Serial Peripheral Interface (SPI) is an interface bus commonly used to send data between microcontrollers and small peripherals device.
SPI NAND consists of RAW NAND Flash and a controller providing bad block management, wear leveling of NAND and communication with Host through SPI interface.
SPI NAND provides low pin count and smaller dimension compared to parallel NAND Flash, which saves design cost and PCB cost of system. The controller of SPI NAND can manage error correction and bad block replacement, it also saves loading of host SOC.
Intelligent Memory (IM) supplies LGA8 6x8mm 8pins package SPI NAND.
1. SPI NAND 's R/W Performance is good enough for boot device rather than large storage
2. SPI NAND can handle ECC and FW complexity, which is easier for SoC to control
3. Overall BOM cost can be reduced in comparison to Parallel NAND
Yes, there are many successful applicaion implemened SPI NAND such as Set Top Box, Wi-Fi Router, Surveillance Camera, NVR, Smart Home devices...
TBW (Terabytes Written) is a measurement of SSDs' expected lifespan, which represents the amount of data written to the device.
Data Retention is the capability of retaining stored information over time. The Data Retention Time is the period of time the memory can "retain" data in an unbiased condition. Also, data retention time is a function of P/E cycles and temperature. On the other side, NAND Flash Endurance and TBW highly depend on data retention period required.